Loads, Stores, and Transfers
Arithmetic Operations
Logical Operations
Data Testing and Bit Manipulation
Shifts and Rotates
Stack and Index Register Instructions
Condition Code Register Instructions
Branches, Jumps, and Subroutines
Interrupt Handling
Miscellaneous Instructions
| Addressing Mode [Cycles to complete] | ||||||||
|---|---|---|---|---|---|---|---|---|
| Function | Mnemonic | REL | IMM | DIR | EXT | INDX | INDY | INH |
| Clear Memory Byte | CLR | - | - | - | 6 | 6 | 7 | - |
| Clear Accumulator A | CLRA | - | - | - | - | - | - | 2 |
| Clear Accumulator B | CLRB | - | - | - | - | - | - | 2 |
| Load Accumulator A | LDAA | - | 2 | 3 | 4 | 4 | 5 | - |
| Load Accumulator B | LDAB | - | 2 | 3 | 4 | 4 | 5 | - |
| Load Double Accumulator D | LDD | - | 3 | 4 | 5 | 5 | 6 | - |
| Pull A from Stack | PULA | - | - | - | - | - | - | 4 |
| Pull B from Stack | PULB | - | - | - | - | - | - | 4 |
| Push A onto Stack | PSHA | - | - | - | - | - | - | 3 |
| Push B onto Stack | PSHB | - | - | - | - | - | - | 3 |
| Store Accumulator A | STAA | - | - | 3 | 4 | 4 | 5 | - |
| Store Accumulator B | STAB | - | - | 3 | 4 | 4 | 5 | - |
| Store Double Accumulator D | STD | - | - | 4 | 5 | 5 | 6 | - |
| Store Double Accumulator D | STD | - | - | 4 | 5 | 5 | 6 | - |
| Transfer A to B | TAB | - | - | - | - | - | - | 2 |
| Transfer A to CCR | TAP | - | - | - | - | - | - | 2 |
| Transfer B to A | TBA | - | - | - | - | - | - | 2 |
| Transfer CCR to A | TPA | - | - | - | - | - | - | 2 |
| Exchange D with X | XGDX | - | - | - | - | - | - | 3 |
| Exchange D with Y | XGDY | - | - | - | - | - | - | 4 |
| Addressing Mode [Cycles to complete] | ||||||||
|---|---|---|---|---|---|---|---|---|
| Function | Mnemonic | REL | IMM | DIR | EXT | INDX | INDY | INH |
| Add Accumulators | ABA | - | - | - | - | - | - | 2 |
| Add Accumulator B to X | ABX | - | - | - | - | - | - | 3 |
| Add Accumulator B to Y | ABY | - | - | - | - | - | - | 4 |
| Add with Carry to A | ADCA | - | 2 | 3 | 4 | 4 | 5 | - |
| Add with Carry to B | ADCB | - | 2 | 3 | 4 | 4 | 5 | - |
| Add Memory to A | ADDA | - | 2 | 3 | 4 | 4 | 5 | - |
| Add Memory to B | ADDB | - | 2 | 3 | 4 | 4 | 5 | - |
| Add Memory to D (16 Bit) | ADDD | - | 4 | 5 | 6 | 6 | 7 | - |
| Compare A to B | CBA | - | - | - | - | - | - | 2 |
| Compare A to Memory | CMPA | - | 2 | 3 | 4 | 4 | 5 | - |
| Compare B to Memory | CMPB | - | 2 | 3 | 4 | 4 | 5 | - |
| Compare D to Memory (16 Bit) | CPD | - | 5 | 6 | 7 | 7 | 7 | - |
| Decimal Adjust A (for BCD) | DAA | - | - | - | - | - | - | 2 |
| Decrement Memory Byte | DEC | - | - | - | 6 | 6 | 7 | - |
| Decrement Accumulator A | DECA | - | - | - | - | - | - | 2 |
| Decrement Accumulator B | DECB | - | - | - | - | - | - | 2 |
| Increment Memory Byte | INC | - | - | - | 6 | 6 | 7 | - |
| Increment Accumulator A | INCA | - | - | - | - | - | - | 2 |
| Increment Accumulator B | INCB | - | - | - | - | - | - | 2 |
| Twos Complement Memory Byte | NEG | - | - | - | 6 | 6 | 7 | - |
| Twos Complement Accumulator A | NEGA | - | - | - | - | - | - | 2 |
| Twos Complement Accumulator B | NEGB | - | - | - | - | - | - | 2 |
| Subtract with Carry from A | SBCA | - | 2 | 3 | 4 | 4 | 5 | - |
| Subtract with Carry from B | SBCB | - | 2 | 3 | 4 | 4 | 5 | - |
| Subtract Memory from A | SUBA | - | 2 | 3 | 4 | 4 | 5 | - |
| Subtract Memory from B | SUBB | - | 2 | 3 | 4 | 4 | 5 | - |
| Subtract Memory from D (16 Bit) | SUBD | - | 4 | 5 | 6 | 6 | 7 | - |
| Test for Zero or Minus | TST | - | - | - | 6 | 6 | 7 | - |
| Test for Zero or Minus A | TSTA | - | - | - | - | - | - | 2 |
| Test for Zero or Minus B | TSTB | - | - | - | - | - | - | 2 |
| Multiply (D = A x B) | MUL | - | - | - | - | - | - | 10 |
| Fractional Divide [ X = (D/X) ; D = remainder ] | FDIV | - | - | - | - | - | - | 41 |
| Integer Divide [ X = (D/X) ; D = remainder ] | IDIV | - | - | - | - | - | - | 41 |
| Addressing Mode [Cycles to complete] | ||||||||
|---|---|---|---|---|---|---|---|---|
| Function | Mnemonic | REL | IMM | DIR | EXT | INDX | INDY | INH |
| AND A with Memory | ANDA | - | 2 | 3 | 4 | 4 | 5 | - |
| AND B with Memory | ANDB | - | 2 | 3 | 4 | 4 | 5 | - |
| Bits(s) Test A with Memory | BITA | - | 2 | 3 | 4 | 4 | 5 | - |
| Bits(s) Test B with Memory | BITB | - | 2 | 3 | 4 | 4 | 5 | - |
| Ones Complement Memory Byte | COM | - | - | - | 6 | 6 | 7 | - |
| Ones Complement A | COMA | - | - | - | - | - | - | 2 |
| Ones Complement B | COMB | - | - | - | - | - | - | 2 |
| OR A with Memory (Exclusive) | EORA | - | 2 | 3 | 4 | 4 | 5 | - |
| OR B with Memory (Exclusive) | EORB | - | 2 | 3 | 4 | 4 | 5 | - |
| OR A with Memory (Inclusive) | ORAA | - | 2 | 3 | 4 | 4 | 5 | - |
| OR B with Memory (Inclusive) | ORAB | - | 2 | 3 | 4 | 4 | 5 | - |
| Addressing Mode [Cycles to complete] | ||||||||
|---|---|---|---|---|---|---|---|---|
| Function | Mnemonic | REL | IMM | DIR | EXT | INDX | INDY | INH |
| Bit(s) Test A with Memory | BITA | - | 2 | 3 | 4 | 4 | 5 | - |
| Bit(s) Test B with Memory | BITB | - | 2 | 3 | 4 | 4 | 5 | - |
| Clear Bit(s) in Memory | BCLR | - | - | 6 | - | 7 | 8 | - |
| Set Bit(s) in Memory | BSET | - | - | 6 | - | 7 | 8 | - |
| Branch if Bit(s) Clear | BRCLR | - | - | 6 | - | 7 | 8 | - |
| Branch if Bit(s) Set | BRSET | - | - | 6 | - | 7 | 8 | - |
| Addressing Mode [Cycles to complete] | ||||||||
|---|---|---|---|---|---|---|---|---|
| Function | Mnemonic | REL | IMM | DIR | EXT | INDX | INDY | INH |
| Arithmetic Shift Left Memory | ASL | - | - | - | 6 | 6 | 7 | - |
| Arithmetic Shift Left A | ASLA | - | - | - | - | - | - | 2 |
| Arithmetic Shift Left B | ASLB | - | - | - | - | - | - | 2 |
| Arithmetic Shift Left Double | ASLD | - | - | - | - | - | - | 3 |
| Arithmetic Shift Right Memory | ASR | - | - | - | 6 | 6 | 7 | - |
| Arithmetic Shift Right A | ASRA | - | - | - | - | - | - | 2 |
| Arithmetic Shift Right B | ASRB | - | - | - | - | - | - | 2 |
| (Logical Shift Left Memory) | (LSL) | - | - | - | 6 | 6 | 7 | - |
| (Logical Shift Left A) | (LSLA) | - | - | - | - | - | - | 2 |
| (Logical Shift Left B) | (LSLB) | - | - | - | - | - | - | 2 |
| (Logical Shift Left Double) | (LSLD) | - | - | - | - | - | - | 3 |
| Logical Shift Right Memory | LSL | - | - | - | 6 | 6 | 7 | - |
| Logical Shift Right A | LSRA | - | - | - | - | - | - | 2 |
| Logical Shift Right B | LSRB | - | - | - | - | - | - | 2 |
| Logical Shift Right Double | LSLD | - | - | - | - | - | - | 3 |
| Rotate Left Memory | ROL | - | - | - | 6 | 6 | 7 | - |
| Rotate Left A | ROLA | - | - | - | - | - | - | 2 |
| Rotate Left B | ROLB | - | - | - | - | - | - | 2 |
| Rotate Right Memory | ROR | - | - | - | 6 | 6 | 7 | - |
| Rotate Right A | RORA | - | - | - | - | - | - | 2 |
| Rotate Right B | RORB | - | - | - | - | - | - | 2 |
As mentioned in the M68HC11 Reference Manual, the logical-left-shift instructions are shown in parentheses because there is not difference between an arithmetic and a logical left shift. The mnemonics are recognized by the assembler as equivalent.
| Addressing Mode [Cycles to complete] | ||||||||
|---|---|---|---|---|---|---|---|---|
| Function | Mnemonic | REL | IMM | DIR | EXT | INDX | INDY | INH |
| Add Accumulator B to X | ABX | - | - | - | - | - | - | 3 |
| Add Accumulator B to Y | ABY | - | - | - | - | - | - | 4 |
| Compare X to Memory (16 Bit) | CPX | - | 4 | 5 | 6 | 6 | 7 | - |
| Compare Y to Memory (16 Bit) | CPY | - | 4 | 5 | 6 | 6 | 7 | - |
| Decrement Stack Pointer | DES | - | - | - | - | - | - | 3 |
| Decrement Index Register X | DEX | - | - | - | - | - | - | 3 |
| Decrement Index Register Y | DEY | - | - | - | - | - | - | 4 |
| Increment Stack Pointer | INS | - | - | - | - | - | - | 3 |
| Increment Index Register X | INX | - | - | - | - | - | - | 3 |
| Increment Index Register Y | INY | - | - | - | - | - | - | 4 |
| Load Index Register X | LDX | - | 3 | 4 | 5 | 5 | 6 | - |
| Load Index Register Y | LDY | - | 4 | 5 | 6 | 6 | 6 | - |
| Load Stack Pointer | LDS | - | 3 | 4 | 5 | 5 | 6 | - |
| Pull X from Stack | PULX | - | - | - | - | - | - | 5 |
| Pull Y from Stack | PULY | - | - | - | - | - | - | 6 |
| Push X onto Stack | PSHX | - | - | - | - | - | - | 4 |
| Push Y onto Stack | PSHY | - | - | - | - | - | - | 5 |
| Store Index Register X | STX | - | - | 4 | 5 | 5 | 6 | - |
| Store Index Register Y | STY | - | - | 5 | 6 | 6 | 6 | - |
| Store Stack Pointer | STS | - | - | 4 | 5 | 5 | 6 | - |
| Transfer SP to X | TSX | - | - | - | - | - | - | 3 |
| Transfer SP to Y | TSY | - | - | - | - | - | - | 4 |
| Transfer X to SP | TXS | - | - | - | - | - | - | 3 |
| Transfer Y to SP | TYS | - | - | - | - | - | - | 4 |
| Exchange D with X | XGDX | - | - | - | - | - | - | 3 |
| Exchange D with Y | XGDY | - | - | - | - | - | - | 4 |
| Addressing Mode [Cycles to complete] | ||||||||
|---|---|---|---|---|---|---|---|---|
| Function | Mnemonic | REL | IMM | DIR | EXT | INDX | INDY | INH |
| Clear Carry Bit | CLC | - | - | - | - | - | - | 2 |
| Clear Interrupt Mask Bit | CLI | - | - | - | - | - | - | 2 |
| Clear Overflow Bit | CLV | - | - | - | - | - | - | 2 | Set Carry Bit | SEC | - | - | - | - | - | - | 2 |
| Set Interrupt Mask Bit | SEI | - | - | - | - | - | - | 2 |
| Set Overflow Bit | SEV | - | - | - | - | - | - | 2 |
| Transfer A to CCR | TAP | - | - | - | - | - | - | 2 |
| Transfer CCR to A | TPA | - | - | - | - | - | - | 2 |
| Addressing Mode [Cycles to complete] | ||||||||
|---|---|---|---|---|---|---|---|---|
| Function | Mnemonic | REL | IMM | DIR | EXT | INDX | INDY | INH |
| Branch if Carry Clear [C = 0 ?] | BCC | 3 | - | - | - | - | - | - |
| Branch if Carry Set [C = 1 ?] | BCS | 3 | - | - | - | - | - | - |
| Branch if Equal Zero [Z = 1 ?] | BEQ | 3 | - | - | - | - | - | - |
| Branch if Great Than or Equal [Signed >= ] | BGE | 3 | - | - | - | - | - | - |
| Branch if Great Than [Signed > ] | BGT | 3 | - | - | - | - | - | - |
| Branch if Higher [Unsigned > ] | BHI | 3 | - | - | - | - | - | - |
| Branch if Higher or Same (same as BCC) [Unsigned >= ] | BHS | 3 | - | - | - | - | - | - |
| Branch if Less Than or Equal [Signed <= ] | BLE | 3 | - | - | - | - | - | - |
| Branch if Lower (same as BCS) [Unsigned < ] | BLO | 3 | - | - | - | - | - | - |
| Branch if Lower or Same [Unsigned <= ] | BLS | 3 | - | - | - | - | - | - |
| Branch if Less Than [Signed < ] | BLT | 3 | - | - | - | - | - | - |
| Branch if Minus [N = 1 ?] | BMI | 3 | - | - | - | - | - | - |
| Branch if Not Equal [Z = 0 ?] | BNE | 3 | - | - | - | - | - | - |
| Branch if Plus [N = 0 ?] | BPL | 3 | - | - | - | - | - | - |
| Branch if Bit(s) Clear in Memory Byte [Bit Manipulation] |
BRCLR | - | - | 6 | - | 7 | 8 | - |
| Branch Never [3-cycle NOP] | BRN | 3 | - | - | - | - | - | - |
| Branch if Bit(s) Set in Memory Byte [Bit Manipulation] |
BRSET | - | - | 6 | - | 7 | 8 | - |
| Branch if Overflow Clear | BVC | 3 | - | - | - | - | - | - |
| Branch if Overflow Set | BVS | 3 | - | - | - | - | - | - |
| Jump | JMP | - | - | - | 3 | 3 | 4 | - |
| Branch to Subroutine | BSR | 6 | - | - | - | - | - | - |
| Jump to Subroutine | JSR | - | - | 5 | 6 | 6 | 7 | - |
| Return from Subroutine | RTS | - | - | - | - | - | - | 5 |
| Addressing Mode [Cycles to complete] | ||||||||
|---|---|---|---|---|---|---|---|---|
| Function | Mnemonic | REL | IMM | DIR | EXT | INDX | INDY | INH |
| Return from Interrupt | RTI | - | - | - | - | - | - | 12 |
| Software Interrupt | SWI | - | - | - | - | - | - | 14 |
| Wait for Interrupt | WAI | - | - | - | - | - | - | ** |
**As mentioned in the M68HC11 E Series Technical Data Document, 12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-Clock cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).
| Addressing Mode [Cycles to complete] | ||||||||
|---|---|---|---|---|---|---|---|---|
| Function | Mnemonic | REL | IMM | DIR | EXT | INDX | INDY | INH |
| No Operation (2-cycle delay) | NOP | - | - | - | - | - | - | 2 |
| Stop Clocks | STOP | - | - | - | - | - | - | 2 |
| Test | TEST | - | - | - | - | - | - | ** |
**Infinity or until reset occurs.
