Present - Senior Principal Design Engineer for Standard Microsystems Component Products division.
1979-Present Developed Custom integrated circuits (ASICS) and continuing cell library development.
1999-2000 Jane has been doing most of the cell library development under my supervision. Most of our chips are doing 5-8KV of ESD on all pins including power pins. I can't help but wonder how you guys at AT&T and IBM are doing, cause I've got this nailed. We have chips passing 8KV on all pins including power supplies and then passing final test at 0.3um and 0.25um. Jane has freed me up to release USB - OHCI controller in southbridge chip and followup core chip sets. The OHCI controller is a Verilog HDL based design. Most recent work is cranking out Advanced I/O products for PC motherboard applications (sort of like making cookies if you didn't know.)
- 1998 - Completed 0.35 micron Cell Library
- Added anti back drive circuits to many PAD cells in 0.5 micron Cell Library.
Completed development of Embedded Low Speed/High Speed Usb buffer and added to 0.5 micron cell library.
Awarded Bridge Mode Patent - a method for testing and accessing Embedded Devices that are controlled by an Embedded MicroProcessor without the intervention of the Embedded Microprocessor.
- 1997 - Developed USB Serial Interface Engine (SIE) in VHDL
- Interfaced SIE to Memory Management Unit (MMU)and 8051 Embedded Micro Processor Unit (MMU). Helped debug silicon, made revisions to enhance interface with MPU and added Simple Host Emulation Capability. Trained replacement on USB device, operation, testing, protocol. Worked with replacement on Embedded USB HUB interfacing to Embedded SIE with two external ports.
Awarded patent for Low Power (2uA) POR circuit with enhanced retriggering.
Promoted to Senior Principal Design Engineer.
1995 - Developed Serial IRQ as used in Super and Ultra IO devices.
Architected Bridge Mode to bypass 8051 into it's memory space - Patent filed and Pending.
Worked on MPU (8051) enhancements added Int5 and Int6 plus other features.
1994,5 - Served on ISO9000 Auditing Team.
- Developed Low Current POR circuits (less than 3uA worst case @ 5.5v)- a Patent has been Filed and is Pending
- This circuit continuously monitors the power supply voltage for stability and retriggers the POR signal when necessary.
- Developed Low Noise - High Current Output Buffers with Short Circuit Protection - Patent Granted
- Drives gently to that desired DC level without that killer ground switching spike and yet meets the required DC level with room to spare.
- Developed World Class Standard Cell Libraries for SMC component division including:
- 1.6u, 1.2u, 0.8u, 0.6u, 0.5 and 0.35 - All SMC component chips in production today rely on the accuracy of these cell libraries. Pad cells boast 5KV ESD and plus/minus 300mA current without latchup at preferred wafer foundries. Libraries support multiple power and ground supplies at the schematic level through to netlisting, back annotated timing, and circuit files for LVS. Efforts in cell library development are ongoing.
- 1989 - Developed first standard product Super IO. Ultra IO product support as required.
- 1988 - Floppy Disk Controller - archetected enhancement to increased address space and simplified addressing modes by increasing width of instruction word; also original conversion from custom core to standard cells. Debugged the ELANC (Local Area Network Controller).
- 1987 - Transferred to Standard Products group as Principal Design Engineer. Debugged and solved ARCNET yield problems.
- 1981-1986 as Manager of Custom Products, managed IC design group, IC test group, layout design, and a design automation group which grew to over 25 people.
- Early 80s - Patent granted for Low Current NMOS - Depletion Mode Storage Element.
- 1979-1981 as Senior Design Engineer, developed custom LSI in Custom Products Division. Designed the game chip for the Game of Generals.
