Min
Max Min
Maxvoltage
voltage
Schmitttrigger
spikes that must
be suppressed
voltage
bus-pins
each bus-pin
ABOUT THE I²C Bus
2.1) Historical background. The I²C bus was developed in the early 1980's by Philips semiconductors.It's purpose was to provide an easy way to connect a CPU to peripheral chips in a TV-set. Normal Computer systems use ByteWide buses to accomplish this task. This results in lots of copper tracks on PCB's to route the Address and datalines. Not to mention a bunch of address decoders and glue logic to connect everything.In mass production items such as TV-sets, VCR's and audio equipment this is not acceptable.Furthermore lots of control lines implies that the systems is more susceptible to disturbances by EMC and ESD.The research done by Philips Labs in Eindhoven (The Netherlands) resulted in a 2 wire communication bus called the I²C bus. I²C is an acronym for Inter-IC bus.It's name literally explains it's purpose: to provide a communication link between Integrated Circuits. Nowadays the extent of the bus goes much further than Audio and Video equipment.The bus is generally accepted in industry.Offsprings like D2B and ACCESS bus find their ways into computer peripherals like keyboards,mice,printers,monitors,etc... . The I²C Bus has been adopted by several leading chip manufacturers like Xicor,SGS-Thomson,Siemens, Intel,TI,Maxim,Atmel,Analog Devices. 2.2) I²C Bus protocol The BUS physically consists of 2 active wires and a ground connection. The active wires ,SDA en SCL,are both bi-directional. Where SDA is the Serial DAta line and SCL is the Serial CLock line. Every component hooked up to the bus has its own unique address whether it is a CPU,LCD driver,memory,or complex function chip.Each of these chips can act as a receiver and/or transmitter depending on it's functionality.Obviously an LCD driver is only a receiver ,while a memory or I/O chip can both be transmitter and receiver. Furthermore there may be one or more BUS MASTER's. The BUS MASTER is the chip issuing the commands on the BUS. In the I²C protocol specification it is stated that the IC that initiates a data transfer on the bus is considered the BUS MASTER. At that time all the others are regarded to as the BUS SLAVEs. As mentioned before , the IC bus is a Multi-MASTER BUS. This means that more than one IC capable of initiating data transfer can be connected to it. As MASTERs are generally microcomputers let's take a look at a general 'inter-IC chat' on the bus. Lets consider the following setup :
Case : The CPU wants to talk to the I/O port.
The CPU will issue a START condition
(see further on for description of all these conditions)
This acts as an 'ATTENTION' signal to all of the connected
IC's.ALL IC's on the bus will listen to the bus for incoming
data.
Then the CPU sends the address of the device he wants to
address.This takes 8 clock pulses. At this moment in time all
IC's will compare this address with their own.If it doesn't
match they simply do nothing and wait until the bus is released
by the STOP condition.If the address matches however the chip
will produce a response on the ACKNOWLEDGE signal of the CPU.
The ACKNOWLEDGE signal is issued by the CPU.When the chip which
address matches sees the ACKNOWLEDGE on the bus it Pulls the
data line LOW. This is an indication to the CPU that there is
a chip with the wanted address on the bus.
Now the CPU can start transmitting or receiving data
In our case the CPU will transmit data.When all is done the
CPU will issue a STOP condition. This is a signal that the bus
has been released and that the IC's may expect another
transmission to start any moment.
We have had several states on the BUS right now :
START, address ,ACKNOWLEDGE ,DATA ,STOP. These are all unique
conditions on the BUS.Before we take a closer look into these I will
talk about the hardware of the BUS.This is necessary to understand what
physically is going on.
2.3 Hardware layout of the I²C bus.
As stated before the BUS consists of 2 active signal lines and a ground
potential. Internally in the chip the bus looks like this :
The bus interface is built around an input buffer
and an open drain or open collector transistor.
When nothing happens the bus lines are in the
logic HIGH state. Note here that an external
PULL-UP resistor is necessary. This is an error
that most beginners make.
To put something on the BUS the chips drives its
output transistor , thus pulling the BUS to a LOW
level.
When the bus is IDLE ( nothing going on ) both
lines are HIGH . The HIGH state is defined as NOT
LOW (obvious isn't it) . What I mean here is that you cannot set a
voltage on the HIGH Level. It depends on the supply voltage of the
connected IC's.However as this is mostly 5 Volts you can say that HIGH
is 5 volts and LOW 0 volt.
Nowadays there even exist 3.3 volt IC's. It's clear that in this case
the high level will be 3.3 volts.
2.4 Events on the BUS
We have already mentioned some things like START,STOP,ACKNOWLEDGE,
SLAVE,MASTER and so on. In this section these things get explained.
When reading this you must keep the following 2 things in mind.
- A MASTER is the device that initiates a message. Thus controls the
Clock line. The MASTER always generates the Clock pulses.
- The SDA and SCL lines can only be PULLED low. They cannot be DRIVEN
high. To make them high the device just releases the line.
The external pull-up resistor does the rest of the work.
2.4.1 Start And Stop condition.
A start condition looks like this:
The chip issuing the Start condition first
pulls the SDA (data) line low. And next
pulls the SCL (clock) line low.
A Stop is just the mirror of the above.
The Bus MASTER first releases the SCL and
then the SDA line
The start condition acts as a signal to all connected IC's that
something is about to be transmitted on the BUS.The Stop condition
tells the connected chips that the message has been completed.
2.4.2 Putting something on the BUS.
Putting a bit of any kind on the bus looks like this :
First the MASTER sets the data line
to the appropriate level by pulling
or not pulling the SDA line low.
Then it releases the SCL line for
some time and pulls it low again
before changing the state of the
SDA line.
This is necessary because not all chips on the bus are EDGE driven.
The DATA must stay valid during the HIGH level of the CLOCK pulse.
The only time the DATA line is allowed to change during the HIGH
state of the clock is in a START or STOP condition.
Using the above information ,a transfer could look like this :
SDA H -\ /---\ /---\ /---\ /---\ /---
L \-----/ \---/ \--------/ \-------/ \----/
SCL H ----\ /-\ /-\ /-\ /-\ /-\ /-\ /------
L \---/ \-----/ \---/ \--/ \--/ \--/ \--/
! START ! 1 ! 1 ! 0 ! 1 ! 0 ! 1 ! STOP
As you can see in the above it is not necessary to have a clock with
a constant duty cycle.The BUS is very relaxed even in such a way that
you can stop the clock in the middle of a transaction and then
continue later on. This is very useful. Consider the following :
Your CPU is in the middle of a transaction and gets an interrupt.
It can process the interrupt first and continue its message later on
without any problem. (try doing that on RS232 !).
Since there is no minimum clock speed set you can have the
communication running at whatever speed you can handle.
2.4.3 Addressing a chip.
EVERY byte put on the BUS MUST be 8 bits long. (8 clock pulses)
A byte is always sent with the MSB first.
The number of bytes that can be transmitted in one data 'telegram' is
unrestricted. ('Data telegram' is everything going on on the bus
between a START and STOP condition).
However it is allowed to end a transmission any time by sending a STOP
condition. Even when you are only 4 bits far in your telegram.
Actually what happens is that the STOP condition resets the bus
control logic of all connected chips. They start looking for a START
condition again.
Waiting for ACKNOWLEDGE.
When a chip is being addressed or has received data it will issue an
ACKNOWLEDGE pulse. Therefore the MASTER must release the DATA line
(set it to high level) and then release the CLOCK line. Now it must
wait for the SLAVE to pull the DATA line low. Actually on the bus this
looks like a START condition so nothing happens because of the fact
that the IC's that have not been addressed are doing nothing.(they are
waiting for a STOP condition remember ?)
When the SLAVE has pulled this line low the MASTER will take the CLOCK
line low and then the SLAVE will release the SDA (data) line.
Now that the MASTER knows that the SLAVE is actually there it can
continue. Generally the MASTERs (mainly CPU's running software) use a
timeout value. When no chip is responding after some time they issue a
STOP and then continue with their work.This prevents your software
from locking up if for some reason the addressed chip is not replying.
Concerning the SLAVE pulling low the SDA line it is so that generally
the addressed IC will already have pulled the SDA line low even before
the MASTER has set the clock HIGH.
This is how theoretically it should work
SDA H -\ /--------------------------------\ /--------
L \-/\--------------------------------/\------/\--------
SCL H ----\ !-! !-! !-! !-! !-! !-! !-! !-! !-! !-! !-! !
L \-! !-! !-! !-! !-! !-! !-! !-! !----! !---! !-! !-!
START ! ! !
! ! !
! ! !
addressed SLAVE pulls SDA LOW ---! ! !
CPU checks if SDA is LOW -------! !
addressed SLAVE releases SDA -------------
In the real life it is good practice to actually look during the high
level of the CLOCK if the SDA is being pulled LOW or is LOW.
Some chips need some time to process the address before they can
respond by pulling the SDA low. This can be the fact when the
addressed SLAVE is another CPU or an EEPROM.
Suppose the following : You address a SLAVE CPU. But just before the
SLAVE CPU can pull the SDA low it has to process some interrupt
occurring.If the transfer issuing CPU would look to the SDA line
immediately it would see a HIGH level. Thus it would look like the
SLAVE is not responding.
The Same goes for EEPROM's. Since storing data to EEPROM cells takes
some time the ACKNOWLEDGE is used to indicate that the programming has
been completed. So after the last bit has been transferred the EEPROM
starts writing the received data into it's array.It leaves the SDA
line in the HIGH state until this action has been completed.
I have once spend a whole day figuring this one out !.The system once
in a while did not work like it should have because the addressed
device was not capable of generating an ACKNOWLEDGE in time.
The best way to do an ACKNOWLEDGE ,in my humble opinion,is like this:
Put the SCL high , wait some time (your TIMEOUT value) , then check if
SDA is LOW.
If it is LOW - > The chip is there. If it is HIGH -> The chip isn't
there.If you are writing to EEPROM's then take a bigger TIMEOUT value
in account.
2.4.4 What happens next?
Now that the SLAVE has been addressed and responded to the ACKNOWLEDGE
the rest of the telegram (until we issue a STOP) depends solely on the
addressed chip. You can just send one or more bytes to the chip or
receive one or more bytes from the chip. It can even be that you first
write something and then read something from the chip.
2.4.5 Writing One or more byte's.
After the Device has responded with an ACKNOWLEDGE (see above) you
just send another 8 bits on the bus. Now you have to wait again for
the SLAVE to ACKNOWLEDGE. If you are through you issue a STOP command
and then the bus is released again.
If you need to send more then you just send another 8 bits and wait
for an ACKNOWLEDGE. And so on and on and on.
I figured out in real life that on the last transmitted byte you do
not have to wait for the ACKNOWLEDGE. You can directly issue a STOP
command.Apparently there are some chips that do not generate an
ACKNOWLEDGE here !.
Theoretically they should generate an ACKNOWLEDGE but for some reason
they don't. The best way is as follows : after you have transferred
your last byte just to set the SCL high , wait some time , take it low
and then issue a STOP command.There is an exception though. Devices
like serial EEPROM's use the ACKNOWLEDGE for storing the information in
the Memory array.They do not pull the SDA line low until the
programming has been completed.In that way the MASTER has a way to
know if the data has been written successfully.Storing data in eeprom
memory is rather slow.So by monitoring the SDA line the CPU knows when
the chip has completed the WRITE to its memory array.
A byte write could look like this :
-----------------------------------------
! S ! SLAVE address ! WA ! DATA ! WA ! P !
-----------------------------------------
A multi byte write looks like this:
----------------------------------------------------------------------
! S ! SLAVE addr. ! WA ! DATA ! WA ! DATA ! WA !.....! DATA ! WA ! P !
----------------------------------------------------------------------
Note : S = START
WA = WAIT FOR ACKNOWLEDGE
P = STOP
2.4.6 Reading a byte.
Looks kind of the same as a byte write. The difference is the handling
of the SDA line and the ACKNOWLEDGE.
The MASTER generates a START , transmits the device address and waits
for an ACKNOWLEDGE. So far so good. Now the MASTER has to RELEASE the
SDA (data) line. The SLAVE will pull it low when needed. On every
clock pulse , that the MASTER generates ,the SDA line will be in the
state set by the SLAVE.When all 8 bits have been read the MASTER must
GIVE the ACKNOWLEDGE to the SLAVE .
This goes as follows:
---------------------------------------------------
! S ! address SLAVE ! WA ! READ 8 BITS ! GA ! STOP !
---------------------------------------------------
GA = Give ACKNOWLEDGE.
What physically happens is the following
SDA H /-------------------------------\/--\ /--
L ----/\-------------------------------/ \--------/
SCL H --\ !-! !-! !-! !-! !-! !-! !-! !-! /-\
L \--! !-! !-! !-! !-! !-! !-! !-! !-------/ \------
ACK ! MASTER controls SCL ! ! !
BY ! SLAVE controls SDA ! *1 ! *2 ! *3
SLAVE! ! ! !
*1 : The SLAVE releases SDA (SDA goes HIGH)
*2 : The MASTER first pulls SDA low then gives a CLOCK pulse
and releases SDA again.(SDA goes back high)
This acts as a signal to the SLAVE that the MASTER has received
all 8 bits.
*3 : Depending on what happens next. A stop condition could be issued
by the MASTER. Or another byte could be read.
Confused ? keep these rules in mind :
The chip controlling the CLOCK is the MASTER .
all others are SLAVES at that moment.
Now go and read the above again. (from Reading a BYTE on)
When you are reading another byte you just give another 8 clock
pulses and then generate an ACKNOWLEDGE again. (note that it is
the MASTER here that must generate the ACKNOWLEDGE ).
Reading one Byte
----------------------------------------------
! S ! SLAVE address ! WA ! READ BYTE ! GA ! P !
----------------------------------------------
or
-----------------------------------------
! S ! SLAVE address ! WA ! READ BYTE ! P !
-----------------------------------------
Since STOP resets all SLAVEs why bother about giving an ACKNOWLEDGE ?.
This works fine in practical applications.
Reading a sequence of bytes.
----------------------------------------------------------------------
! S ! SLAVE address ! WA ! READ BYTE ! GA !....! READ BYTE ! GA ! P !
----------------------------------------------------------------------
or
----------------------------------------------------------------
! S ! SLAVE address ! WA ! READ BYTE ! GA !....! READ BYTE ! P !
----------------------------------------------------------------
2.4.7 Determining the SLAVE Access mode.
Now there is one thing I haven't told you yet. How does your SLAVE
know whether you want to read from or write to it ?
That's an easy one. This is being determined by the SLAVE address.
Each byte consists of 8 bits. The 8th bit in the SLAVE address has a
special meaning. When it is set to 0 it means you want to write to
your SLAVE. When it is set to 1 it means that you you want to READ.
You could see this as follow. The Even addresses are WRITE addresses,
the ODD addresses are READ addresses. Each device has a consecutive
WRITE and READ address.
Example : a PCF8574 General purpose 8 BIT I/O port.
SLAVE address to WRITE is (01000000)b = 64d
SLAVE address to READ is (01000001)b = 65d
So you can have a theoretical maximum of 128 device on you BUS.
Practically this is not the case. There have been set up a couple of
addresses which you are not allowed to use.(more about this later on)
Still following ?
Now there is one more type of DATA telegram.
2.4.8 The Combined data format.
This is a format generally used by memory devices .
Suppose you have an 128 byte deep memory on the bus and you want to
read the 84th byte. Normally you would have to read the first 83 bytes
before getting what you want.This takes too much time and occupies the
bus. In this case there are two possibilities.
You first write to the SLAVE address a byte which tells it on which
location you want to read. Then you start a read operation.
That is one way of doing it.
A more elegant way to do this is using a combined mode telegram.
--------------------------------------------------------------------
! S ! AS WRITE ! WA ! SEND BYTE ! WA ! S ! AS READ ! WA ! READ ! P !
--------------------------------------------------------------------
So you start out as a normal WRITE operation.
AS WRITE = Address Slave in WRITE mode (even address)
Wait for ACKNOWLEDGE and WRITE a byte . This byte is being treated
by the memory as the location pointer. (that is how I²C memories work)
Then you wait for an ACKNOWLEDGE by the SLAVE and you generate another
START condition. Now you send the SLAVEs READ address ( ODD address )
Wait for ACKNOWLEDGE and you receive the data byte. From now on
you are in standard READ mode. So you can now send a STOP or continue
reading from your SLAVE. All memory devices auto-increment their
location pointer.
Now you can even go one step further and generate another START and
then address the SLAVE as write. Send a new Data byte (which acts on
the location pointer), send another start, enter read mode etc ......
This combined mode is really a very flexible means of addressing
complex components.
You can easily do the following in one telegram.
START ,address SLAVE , set location pointer, read ,read ,
set location pointer ,read , set location pointer , write ,
set location pointer ,read , STOP.
This may look very messy . But it has its pro's and con's.
PRO : If you have 2 CPU's on your bus which could want to take the bus
this will assure you that you will be able to continue your
actions on the bus without interference from the other CPU.
Remember that when you have generated a START and have sent the
SLAVE address the other CPU too will be waiting until a STOP
appears on the bus. So he will not try to put something on the
bus.
There could be a risk involved using normal READ and WRITE
operations
Picture this situation :
CPU 1 accesses the MEMORY and sets the location pointer to 84
Now the BUS is FREE.
CPU 2 sees this and thinks : okay my turn.
he sets the location pointer to 92 because he wants to do
something at that location.
Now the bus is free again.
CPU 1 says : aha ! the bus is free. Time to write for me.
Now the data will land on location 92 and not on location 84
as it should have been.
So : If you are dealing with memories always use this last method.
It keeps you out of trouble.
CON:
If you have lots of operations to do you can create a bottleneck
situation. The other CPU could be waiting and waiting for a
chance to have his turn on the bus.
Still with me ?
Congratulations you have reached the EXPERT grade. :-)
2.5 MULTIMASTER communication.(collision detection)
As stated above you can have more than one CPU on the BUS.
When you have only one CPU there are no risks of having collisions on
the bus.
That situation changes with 2 CPU's.
When CPU 1 issues a START and sends an address the other one will back
off. Because of the fact that if the address does not match his own
address he has to wait until the bus is free. (STOP condition). So far
no problem.
But as Murphy is, as usual ,always around. It's when you least expect
it that it goes wrong.Fortunately the BUS setup helps us out here.
When you (as a MASTER ) change the state of a line, you MUST always
check that it has gone to the level you wanted.
If it hasn't : BACKOFF ! it's occupied !.
What could happen is that the TWO CPU's start communication on the
same moment in time.Since it is an open collector/drain bus they can
only PULL the line low. They cannot force it HIGH. (they can only
leave it HIGH by not turning on their output transistor).
So they start transmitting. And all goes well as long as they both are
asserting the same levels. (during START it's okay .They are doing the
same) Then they start asserting a SLAVE address. The first CPU wants
to access SLAVE address 84 and the second CPU wants SLAVE address 87
(for example).So all goes well until they arrive at the 7th bit in the
SLAVE address.
note : 84 = 01010100 (CPU 1)
87 = 01010111 (CPU 2)
!!
---- these are different.
Now CPU 1 has pulled SDA LOW.
CPU leaves SDA open.
Since they are both running clean and good written code they are
testing what they have put on the BUS. CPU 1 sees that he has written
a 0 and says OKAY. CPU 2 on the other hand sees that the line is LOW
while he has left it HIGH :> COLLISION. BACK OFF !.
CPU 1 hasn't even seen this so he just continues whatever he was doing.
Now CPU2 has to check that the slave address being put on the bus is
not his own. If it is nit his own he has to wait for the STOP command to
appear on the bus before attempting to take control again.
On the other hand. If the address is his own address he must respond.In the
latter case CPU2 becomes the slave device on the bus.
This way all ends up well.
So from the above story we can conclude that is the one that has it's
line LOW that always wins.The One which wanted the line to be HIGH when
it is being pulled low by the other looses the BUS .We call this a
loss of arbitration.
When a BACKOFF situation is generated it is good practice to have the
CPU ,that has to BACKOFF ,wait for a STOP condition to appear on the
bus.The other one is still busy transmitting .
Getting the hang of it ?.
You are ready to face the world of I²C. :-)
2.6 Special cases and exceptions.
During the above I have mentioned that there are some exceptions about
device addressing. Not all addresses can be used. There are some that
have been reserved by PHILIPS for special purposes.
address R/W
0000 000 0 : general call address
0000 000 1 : start byte
0000 001 x : CBUS address
0000 010 x : address reserved for different bus format.
0000 011 x !
0000 100 x !
0000 101 x !} to be defined
0000 110 x !
0000 111 x !
This implements that all addresses below 16 are reserved for special
purposes
The reason behind this is that there are other buses around. Using
this scheme you can connect device that uses a different bus
to the I²C bus !.
It is possible to put SPI,I²C,uWIRE and CBUS devices on the same I/O
pins of your CPU. Since all buses different to I²C use 3 lines you can
cut down on you CPU pin load using the following setup :
-------
! CPU !
! !------o--------o---------o--------o-----------------------
! ! ! ! ! !
! !------!-o------!-o-------!-o------!-o----------------------
! ! ! ! ! ! ! ! ! !
! !------!-!-o----!-!-------!-!------!-!-o---------------------
! ! ! ! ! ! ! ! ! ! ! !
! ! ! ! ! ! ! ! ! ! ! !
------- ! ! ! ! ! ! ! ! ! !
------- ----- ----- -------
! SPI ! !I²C! !I²C! !uWIRE!
------- ----- ----- -------
How this exactly works would lead us too far.Maybe in the future this
will be incorporated. If somebody out there has experience with these
other buses ? Could be interesting .
CBUS is the ancestor of I²C .It was also developed by Philips.
SPI is (c) Motorola
and uWIRE is (c) National Semiconductor
Some general notes about these reserved addresses.
- The general call address is received by all IC's on the bus.
If there is an IC out on the bus that can process this address it will
respond by generating an ACKNOWLEDGE.See Datasheets for info on which
IC use them and why.
You could use this to invoke some special command in a MULTIMASTER
environment. (Like reboot all CPU's or whatever .Since all chips will
respond to it ,it can be used for this purpose. However take care not
to mess up anything else.)
There have been determined some actions on receipt of the General call
address.
When the second Byte in a telegram containing a general call is :
00000110 : This is a RESET condition. All IC's capable of handling a
general call message will reset and reload their SLAVE
address.There are I²C compatible IC that have part of
their address programmable.This allows you to have more
than one IC of a certain type on your BUS. Further about
this later on.
They also set all their internal registers to the power-up
state.
00000010 : The same as above except that you must provide the SLAVE
address.This does not RESET the registers to Power-up
state.
00000100 : Causes all IC's that define their address by hardware to
reload this value.This does not reset internal register.
00000000 : PROHIBITED.
xxxxxxx1 : This is a HARDWARE general call.
You can look to this as a kind of INTERRUPT generated by
an I²C IC.
This can be used in the following condition.:
You have a keyboard controller. Each time a key is pressed
it transmits the following sequence :
----------------------------------------------------
! S ! 0000 0000 ! A ! yyyy yyy1 ! A ! Databyte ! P !
----------------------------------------------------
Where yyyy yyy is its own address.
What will happen is that the MASTER CPU will see the
General call address and see that the device with address
yyyy yyy has something to tell to the CPU.It will read the
next byte.In our case the CPU will know that keyboard
controller yyyyyyy has detected a key and that the
scancode of this key is contained in the received databyte.
All other codes have not been assigned. All I²C IC's are designed
to ignore them. So you are free to use them for whatever.
(I generally use them to debug MULTIMASTER modes).
- NO IC is allowed to generated an ACKNOWLEDGE of the START byte.
- The start byte is used to synchronize Slow devices with fast devices.
- The CBUS address is used in this way :
After sending this address all IC's go into IDLE mode until they
receive a STOP condition. In the mean time you can transfer data using
a complete different protocol on your I²C bus.
2.7) Electrical spec.'s of the I²C Bus.
As the chips designed for an I²C bus can function on different Supply
voltages the following levels have been set.
| Symbol | Unit | Standard mode Min Max |
Fast mode Min Max |
|||
|---|---|---|---|---|---|---|
| Low level input voltage |
Vil | V | -0.5 | +1.5 | -0.5 | +1.5 |
| Relative to VDD | -0.5 | +0.3 Vdd | -0.5 | +0.3 Vdd | ||
| High level input voltage |
Vih | V | +3.0 | Vdd(max)+0.5 | +3.0 | Vdd(max)+0.5 |
| Relative to VDD | 0.7 Vdd | Vdd(max)+0.5 | 0.7 Vdd | Vdd(max)+0.5 | ||
| Hysteresis of Schmitttrigger |
Vhys | V | - | - | 0.2 | - |
| Pulse width of spikes that must be suppressed |
tSP | ns | - | - | 0 | 50 |
| Low level output voltage |
||||||
| At 3mA | Vol1 | V | 0 | +0.4 | 0 | +0.4 |
| At 6mA | Vol2 | V | - | - | 0 | +0.6 |
| Input current of bus-pins |
Ii | µA | 10 | 10 | 10 | 10 |
| Capacitance of each bus-pin |
Ci | pF | - | 10 | - | 10 |
The number of interfaces connected is limited to the number of
available addresses and the load capacitance on the bus.
This capacitance may not be bigger then 400pF. In the new standard
this is preferred to be less than 200pF.
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