Enhanced I²C (FAST mode)

     Since the first I²C spec release (which dates back from 1982) a
     couple of improvements have been made.In 1993 the new I²C spec was
     released.This new spec contains some additional sections covering
     FAST mode and 10 -Bit addressing.
     In this section the Fast mode will be covered , while in the next
     section information about 10 bit addressing is given.

     In the FAST mode the physical bus parameters are not altered.
     The protocol,Bus levels,Capacitive load etc.. remain unchanged.
     However the bitrate has been increased to 400 Kbit/s.
     To accomplish this task a number of changes have been made to timing.

     Since all CBUS activities have been canceled ,there is no
     compatibility anymore with CBUS timing.The development of IC with CBUS
     interface has been stopped. The existing CBUS IC's are being taken out
     of production.

     The input of the FAST mode devices all include Schmitt triggers to
     suppress noise.The output buffers include slope control of the falling
     edges of the SDA and SCL signals.If the power supply of a FAST mode
     device is switched off the BUS pins must be floating so that they do
     not obstruct the bus.

     The pull-up resistor must be adapted. For loads up to 200 pF a resistor
     is sufficient.For loads between 200pf and 400pF a current source is
     preferred.