Yen-Kuang Chen

Research Interests

• Computer architecture to embrace the emerging applications
  • Architecture performance and low power analysis, evaluation, and simulations
  • Array processor design/systolic array design
  • Application specific memory hierarchy
• Application specific hardware/software co-design
  • System and platform architecture for next generation audio-visual computing
  • Architecture and algorithm design in multimedia computing
  • MPEG video encoder optimization
• Multimedia signal processing
  • Video compression and processing (e.g., MPEG-1, MPEG-2, MPEG-4, H.263, H.264, and digital video watermarking)
  • Technologies in intelligent human-computer interface

Education

• Ph.D. in Computer Engineering, Department of Electrical Engineering, Princeton University, 1998.
  • Graduated with highest distinction.
  • Ph.D. dissertation title: True Motion Estimation---Theory, Applications, and Implementation.
  • Advisor: Prof. S.-Y. Kung
  • Minor in Mathematics and Computer Science
• B.S. from EE, National Taiwan University, Taipei, 1992.
  • Graduated with highest distinction.
  • Received Book Coupon Awards (highest distinction) in every semester.

Research Experiences

• Principal Researcher, Exploratory Architecture, Intel Corporation, 4/2007 - present
• Senior Staff Researcher, Exploratory Architecture, Intel Corporation, 4/2003 - 3/2007
  • To study scalable, adaptable, and low-power multi-everywhere (multi-core & multi-threaded) architecture for next-generation applications.
  • Studied emerging recognition, mining, & synthesis algorithms and applications.
  • Built a novel simulation infrastructure to design future system.
  • Designed intelligent cache subsystem.
  
  
• Matrix Manager, Workload and Platform Analysis Group, Intel Corporation, 12/2001 - 3/2003.
  • To study the performance bottleneck in current computers, and design next generation microprocessor/platform.
  • Established Workload and Platform Analysis Group at Intel China Research Center.
  • Simulated platform and analyzed performance of new HCI for countries like China where typing is not an option for many.
  
  
• Staff Researcher, Distributed Signal Processing and Exploratory Architecture, Intel Corporation, 8/1999 - 3/2003.
  • To develop innovative multimedia and Internet applications, study the performance bottleneck in current computers, and design next generation microprocessor/platform.
  • Improved the compression efficiency of MPEG-4 for Internet video streaming.
  • Built the first real-time MPEG-4 Fine Granularity Scalability encoder.
  • Co-developed a software library for MPEG video processing and advanced applications.
  • Improved the performance of multimedia applications and developed energy saving techniques on processors with Hyper-Threading Technology.
  
  
• Senior Researcher, Multimedia and Internet Technology, Intel Corporation, 8/1998 - 8/1999
  • To develop innovative multimedia and Internet applications
  • Built a peer-to-peer infrastructure supporting optimized multimedia data replication and delivery over heterogeneous, distributed computers.
  • Created a virtual-reality teleconferencing system with 3D sound, 3D video, and 3D graphics. Demonstrated in Network+Interop 2000 and rated "the most eye-catching demonstration" by ZDNet.
  
  
• Research Assistant, Princeton University, 9/1994 - 7/1998
  • To develop innovative algorithms and architecture for video processing.
  • Invented algorithms that automatically identify true motion for image segmentation.
  • Proposed an architecture platform that provides high performance and high flexibilities, and requires fewer external memory accesses and I/O operations.
  
  
• Summer Researcher, Mitsubishi Electric, 7/1997 - 8/1997
  • Developed a new scheme for intra/inter mode selection in MPEG encoding.

Honors

1. Best Paper Award, International Conference on Very Large Data Bases, 2005.
   • On cache-conscious frequent pattern mining on a modern processor.
2. Microprocessor Technology Labs Division Recognition Award, Intel Corp, 1999, 2002, 2003, 2005, 2007, 2009, and 2009.
   • For outstanding contributions in the development of video technologies for Internet usage, kernel analysis for Intel architecture, new instructions evangelism---proposal, implementation and IP coverage, the first set of architecture recommendations out of recognition, mining, and synthesis applications, first team to deliver an analysis of throughput computing workloads and validate a new simulation infrastructure for Skylake team, and for taking gather/scatter feature from research to IA architecture.
3. Desktop Platforms Group Division Recognition Award, Intel Corp, 2000.
   • For outstanding effort in deploying industry leading Pentium 4 video technology.
4. George Van Ness Lothrop Honorific Fellowships, Princeton University, 1997-98.
   • The highest award conferrable on graduate students.
5. E-Council's Excellence in Teaching Award, Princeton University, 1998.
   • For demonstrating outstanding and exemplary dedication to his role as a Teaching Assistant and for true commitment to helping students.

Professional Recognitions

1. Selected leading young engineer to attend
   • Germany-American Frontiers of Engineering Symposium, by National Academy of Engineering and Alexander von Humboldt Foundation, 2003.
   • National Academy of Engineering's 2002 Frontiers of Engineering Symposium, 2002.
2. Invited speaker,
   • Emerging Information Technology Conference, 2005.
   • New Technology Business Opportunities Forum, 2005.
   • Sino-American Technology & Engineering Conference, 2004.
   • Workshop on Media and Signal Processors for Embedded Systems and SoCs, 2003.
3. Program chairman,
   • Workshop on Multimedia Signal Processing and Novel Parallel Computing, at IEEE International Conference on Multimedia and Expo, 2009.
   • IEEE/NATEA Conference on New Frontiers in Computing Technology, 2005 & 2007.
   • US-Taiwan High-tech Forum, 2004.
4. Program committee members,
   • IEEE International Workshop on Multimedia Signal Processing, 2009.
   • International Conference on Parallel and Distributed Computing and Networks, 2009.
   • International Conference on Embedded Software and Systems, 2008 & 2009.
   • IEEE Workshop on Signal Processing Systems, 2008 & 2009.
   • International Conference on Multimedia & Expo, 2005, 2006, 2007, 2008, and 2009.
     • Chairman of special session on Processors and Multimedia
     • Chairman of special session on Multi-Core Enabled Multimedia Applications and Standards
     • Chairman of special session on Multimedia Signal Processing on Graphics Processors with Hundreds of Cores
   • IEEE International Conference on Parallel and Distributed Systems, 2008.
   • International Workshop on High Performance Data Mining, 2008.
   • Workshop on Emerging Applications and Many-core Architecture, 2008.
   • International Workshop on Wireless Technologies for Smart Homes, 2008.
   • International Conference on Internet and Multimedia Systems and Applications, 2006, 2007, and 2008.
   • Special Issue of IEEE Micro: Micro's Top Picks from Computer Architecture Conferences in 2007.
   • International Workshop on Smart Living Space, 2007.
   • International Conference on Signal and Image Processing, 2006 & 2007.
   • International Workshop on Embedded Software Optimization, 2006 & 2007.
   • International Conference on Electro/Information Technology, 2006.
   • International Conference on Communications, Circuits and Systems, 2004 and 2006.
   • SPIE Conference on Image and Video Communications and Processing, 2000, 2003, and 2005.
   • SPIE Conference on Visual Communications and Image Processing, 2004.
   • SPIE Conference on VLSI Circuits and Systems, 2003.
   • International Conference on Parallel Processing, 2003.
   • SPIE Conference on Multimedia Storage and Archiving Systems, 1999, 2001, 2002, and 2003.
5. Associate editors,
   • Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 1999-present.
     • Editor of special issue on System-on-a-Chip (SoC) for Multimedia Systems.
     • Editor of special issue on Design and Programming of Signal Processors for Multimedia Communication.
     • Editor of special issue on Multicore Enabled Multimedia Applications and Architecture.
   • IEEE Trans. on Circuit and System I, 2004-2005.
   • IEEE Trans. on Circuit and System for Video Technology, 2008-present.
     • Editor of special issue on Algorithm/Architecture Co-Exploration of Visual Computing on Emerging Platforms, 2009.
   • IEEE Trans. on Multimedia, 2009-present.
6. Guest editor,
   • IEEE Signal Processing Magazine, special issue on Signal Processing on Platforms with Multiple Cores: Part 1 -- Overview and Methodology, 2009.
   • IEEE Signal Processing Magazine, special issue on Signal Processing on Platforms with Multiple Cores: Part 2 -- Design and Applications, 2010.
7. Technical committee member
   • Multimedia Signal Processing, IEEE Signal Processing Society, 2008-present.
   • Multimedia Systems and Applications, IEEE Circuits and Systems Society, 2008-present.
   • Visual Signal Processing and Communications, IEEE Circuits and Systems Society, 2008-present.
   • Design and Implementation of Signal Processing Systems, IEEE Signal Processing Society, 2009-present.
8. Patent committee member on Architecture, Intel Corporation, 2007-present.
9. MPEG (ISO/IEC JTC/SC29/WG11) meeting
   • US delegate, 1999 - 2001.
   • Chairman, MPEG Study on Standard Digital Watermarking Technology ad hoc group 1999-2000.
   • Co-chairman, MPEG-4 Intellectual Property Management and Protection ad hoc group in 1999.
10. IEEE Senior Member since 2002.
11. ACM Senior Member since 2006.

Patents and Publications

• 18 Granted Patents, and 22 Pending Patent Applications.
• 85+ Publications (2 book chapters, 20 journal papers, 54 conference papers, and 13 MPEG contributions).

Other Personal Information

• Contact information: my office, phone numbers, etc.