PROJECTS

  Constructed a simulator for an out of order superscalar processor that

  uses the Tomasulo algorithm and fetch N instructions per cycle. Then find

  the the appropriate number of function units and fetch rate for each

  benchmark. (Please refer data for this project)

Branch Predictors (Using C++, Unix)

  Constructed a branch predictor simulator and use it to design branch

  predictors well suited to the SPECint92 benchmarks.

Cache Design (Using C++, Unix)

  Designed a parametric cache simulator and use it to design data caches

  well suited to the SPECint92 benchmarks.The simulator can model any cache

  with 2C bytes of total data storage, having 2B-byte blocks, and with sets

  of 2S blocks per set (note that S=0 is a direct-mapped and S = C - B is a

  fully associative cache).

Project: 4-bit slice microprocessor design (Using HSPICE, Verilog/VHDL, Cadence)

The following files are layout designs (in .gif format):

The following files are schematic designs (in .gif format):

Project 1: MOS device design, including passive load and active load, with calculations and HSPICE simulations.

Project 2: Different current mirrors and multi-step amplifiers designs. The gain range is from 30 to 3000, wit hcalculations and HSPICE simulations

Project 3: Standard Opamp design, including feedback compensations. Use calculations and HSPICE simulations

CRC-10 Error Correction Code for ATM Packets