VHDL Modeling of ARM7 RISC Processor:
A VHDL Course Project


ARM7 Reference: http://www.arm.com/


TEAM
Members and contact information
Name Email Address Phone Number (Home) Phone Number (Office) Pager Number
Brian Dupaix brian@hwcae.honeywell.com
Fuding Ge fudingge@yahoo.com 480-557-6239 480-965-4097
Ge Wang wgge@asu.edu
Hongzhong Xu hongxu@asu.edu
Michael Gomez michael.gomez@motorola.com 480-829-4944 480-413-5548 1-800-341-0845
Yu Wang yuwang@asu.edu 480-965-5021

Fuding Ge is now at Intel
Ge Wang is now at Maxim
Hongzhong Xu is now at Motorola
Yu Wang is now at Phillips


SPECIFICATIONS
Proposal
proposal.doc
proposal.pdf
PROJECT SOURCE CODE  AND DOCUMENTATION
Package Declarations
Block Name Block Source File Block Testbench 
File		 Block Documentation 
(Word)		 Block Documentation (PDF)
arm7_pkg arm7_pkg
arm7_time_pkg.vhdl arm7_time_pkg

Top Level Instantiation and Architectural Definition
Block Name Block Source File Block Testbench 
File		 Block Documentation 
(Word)		 Block Documentation (PDF)
arm7 arm7

Lower Level Instantiation and Architectural Definitions
Block Name Block Source File Block Testbench 
File		 Block Documentation 
(Word)		 Block Documentation (PDF)
adrsReg adrsReg
alu alu
clkBuf clkBuf
decAndCtrl decAndCtrl
rdReg rdReg
regBank regBank
wdReg wdReg