Important Specifications about these Standard Cells

Process: HP .5 micron CMOS

Voltage: 3 Volts

Timing: 3 ns rise and fall time

Notes on Timing: Timing was measured using SPICE simulation. Timed when the voltage reached within 10% of final value, i.e. 2.7 V for rise time and .3 V for fall time. Since power consumption was an important factor in the application of these standard cells, some of the larger cells will have longer then 3 ns rise and fall times. All timing reflect worst time possible, when only transistor was charging or discharging. The unit capacitance is 1e-13 F (.1 pF), thus a cell with a _4x has a load of .4 pF when tested.

Click here to get the timing file:lpstdcells2.v

Last modified on: December 9, 1999 by Willem-Jan Ouborg

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