Dr. Yaseer A. Durrani has completed his Doctorate/Ph.D. in Industrial Microelectronics Eningeering (DIE), from Polytechnic University of Madrid (UPM), Madrid, Spain. The Dissertation Title is "Power Macro-modelling for IP-based Digital Systems at Register Transfer Level". His research has been invloved in "Statistical Power Estimation, Power Optimization, and Low Power Consumption". His most of the work concentrate on Power Macro-modelling based approach that captures the dependence of the power dissipation of digital electronic circuits on its input/output signal switching statistics. This technique to estimate switching activity and power consumption at the Register Transfer Level (RTL) is for digital intellectual property (IPs) and the System-on-Chip (SoCs). Dr. Durrani is currently working as a Chairman of the Dept. of Electronics & Telecommunicaiton Engineering at University of the Punjab (PU), Lahore, Pakistan. During (2007) he obtained his Post Graduate Research Diploma in Industrial Microelectronic Engineering from Polytechnic University of Madrid, Spain. In (2002) he completed his MSc. in Microelectronics Engineering specializing in System-on-Chip Design (SoC) from Royal Institute of Technology (KTH), Stockholm, Sweden. In (1999) he received his BSc. in "Electrical & Electronics Engineering (EE) from Eastern Mediterranean University (EMU), Turkish Cyprus. Earlier he obtained another BSc. in "Physics & Mathematics" from University of Peshawar, in (1995) (UPESH). Mr. Durrani is the member of Institute of Electrical & Electronics Engineers, (USA) (IEEE), and Pakistan Engineering Council (PEC). He has published technical papers in more than ten international conferences. Dr. Durrani has worked as an Assistant Professor at GIK Institute of Engineering Sciences & Technology (GIKI), Topi, Pakistan. Dr. Durrani was invited as Researcher in University of Victoria, (UVic) Victoria, Canada in (2005) and Ryerson University, Toronto, Canada. During (2001) he worked as a Design Engineer in Fibre Optics department, Infineon Technologies AG, (Infineon) Berlin, Germany for "Optimization of PLL and Serializer on LINC IC based on 0.18 micron CMOS Technology". He also worked as Computer Hardware Engineer in COSMO Computer Works, Pakistan in the field of System Support, Testing & Validation, Soldering, Hardware/Software Troubleshooting and had undergone training in Pak Telecom Company Ltd, Pakistan in Digital Switching Systems. His field of interest is System-On-Chip (SoC) related Low Power Consumption, Power Estimation, Power Optimization, ASIC Design, and Digital Control Systems.

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International Publications

JOURNALS [1] Yaseer A. Durrani, T. Riesgo, Architectural Power Analysis for Intellectual Property-Based Digital System, ASP Journal of Low Power Electronics, (JOLPE), Vol 3, No 3, Dec 2007. [2] Yaseer A. Durrani, T. Riesgo, Power Estimation Technique for DSP Architecture, Elsevier Journal of Digital Signal Processing, (DSP),Vol. 19, Issue 2, pp.213-219, March 2009. CONFERENCES [3] Yaseer A. Durrani, Architectural Power Macromodeling Technique for DSP Architectures, In Proceedings for IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, (DTIS), April 2009, Cairo, Egypt. [4] Yaseer A. Durrani, Accurate power estimation technique for DSP Architectures, In Proceedings for IEEE International Symposium on Industrial Electronics, (ISIE), July 2009, Seoul, Korea. [5] Yaseer A. Durrani, T. Riesgo, LUT-Based Power Macromodeling Technique for DSP Architectures, In Proceedings for IEEE International Conference on Electronics, Circuits and Systems, (ICECS), Dec. 2007, Morocco. [6] Yaseer A. Durrani, A. Abril, T. Riesgo, Efficient power macromodeling technique for IP-based digital system, In Proceedings for IEEE International Symposium on Circuits & Systems, (ISCAS), pp. 1145-1148, May 2007, New Orleans, USA. [7] Yaseer A. Durrani, T. Riesgo, LUT-Based Power Macromodeling Technique for DSP Architectures, In Proceedings for IEEE International Conference on Electronics, Circuits and Systems, (ICECS), Dec. 2007, Morocco. [8] Yaseer A. Durrani, T. Riesgo, Statistical power estimation for IP-based design, In Proceedings for IEEE Conference on Industrial Electronics Society, (IECON), pp. 4935-4939, Nov. 2006,Paris, France. [9] Yaseer A. Durrani, T. Riesgo, Power macromodeling for IP modules, In Proceedings for IEEE International Conference on Electronics, Circuits and Systems, (ICECS), pp. 1172-1175, Dec. 2006, Nice, France. [10] Yaseer A. Durrani, A. Abril, T. Riesgo, Architectural power estimation technique for IP-based system-on-chip, In Proceedings for IEEE International Symposium on Industrial Electronics, (ISIE), June 2007, Vigo, Spain. [11] Yaseer A. Durrani, A. Abril, T. Riesgo, High-level power estimation for digital system, In Proceeding for the SPIE European Symposium on Microtechnologies for the New Millennium ,(SPIE), May 2007, Gran Canaria, Spain. (Invited Paper) [12] Yaseer A. Durrani, T. Riesgo, F. Machado, Statistical power estimation for register transfer level, In Proceedings for International Conference on Mixed Design of Integrated Circuits and Systems, (MIXDES), pp. 522-527, June 2006. Gdynia, Poland. [13] Yaseer A. Durrani, T. Riesgo, Power macromodeling for high level power estimation, In Proceedings for International Workshop on Reconfigurable Communication-Centric System-on-Chip, (ReCoSoC), pp. 232-236, July 2006. Montpellier, France. [14] Yaseer A. Durrani, T. Riesgo, F. Machado, Power estimation for register transfer level by genetic algorithm, In Proceedings for International Conference on Informatics in Control Automation and Robotics, (ICINCO), pp. 527-530, Aug. 2006. Setubal, Portugal. [15] Yaseer A. Durrani, T. Riesgo, Power estimation for IP-based modules, In Proceeding for International Symposium on System-on-Chip, (SoC), pp. 95-98, Nov. 2006, Tampere, Finland. [16] Yaseer A. Durrani, T. Riesgo, High level statistical power estimation, In Proceeding for International Workshop on Symbolic Method and Applications to Circuit Design, (SMACD), Oct. 2006, Firenze, Italy. [17] Yaseer A. Durrani, T. Riesgo, A. Abril, Power macromodeling technique for IP-based system, In Proceeding for International Conference on Design of Circuits and Integrated Systems, (DCIS), Nov. 2006, Barcelona, Spain.

Research Reports

Statistical Power Estimation for Macrocells at Register Transfer Level

Power Optimization of 4x4-Bit Pipelined Array Multiplier

Low Power IC Design Approach

Abstract: Optimization of PLL and Serializer

Detail: Optimization of PLL and Serializer

Layouts: Optimization of PLL and Serializer

Design of Arithmetic And Logic Unit For Microprocessor EMU544

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