Cadence Tutorial - Cadence Basics

View Names:

Abstract: This view is used for cell block ensemble. It is a simplified view of the layout that contains on a rectangle in which contains the cell and the location of the pins. Helps place the cells on the chip, but does not take up much memory.

Config: This view is used to simulate layout. It tells the simulator have view to use, which was in our case the analog_extracted view.

Analog_extracted: This view is created when testing your layout. It is a view used to simulate the circuit that includes capacitance's due to interconnects and other sources not included in schematic simulation.

Compacted: This is a compacted view of the layout. It makes everything as small as possible.

Extracted: Converts the layout to transistors and creates a net list. So instead of just areas of poly and metal etc. the transistors are defined.

Layout: This is the physical layout of the cell. It defines the of areas of poly, metal and dopings etc that will end up being the cell.

Schematic: This view is the transistor level part of the standard cell. Here you can edit the size and wiring of the transistors

Symbol: This is fairly self explanatory, this view contain the logic symbol for the device.

Standard Cell: Standard Cell is a logic device such as an inverter or flip flop etc. What is standard about a standard cell is it's width in the layout, as well as the position of the inputs and outputs. This way long strips can be laid out on the chip. The advantage of this is that programs such as Cadence can be used to automatically create chips from a VHDL or Verilog file using the standard cells as building blocks.

LSI/VLSI/GSI: stands for Large Scale integration, Very large Scale integration and Giga Scale integration. Just refers to the number of transistors on the chip.