Once we have designed our standard cell, we physically layout the transistor. We have several options to how layout our standard cells. We can use the Hand layout option to layout designs by hand, might be used to optimize larger functions such as adders or could also be used for dynamic logic. Analog Cells can be used to design analog compoents such as amplifiers, or other components that might be used in a mixed signal device. We can have Cadence Automatically layout our standard cell as well. Standard Cell creation covers some basic properites of standard cells, such as size and input/output pin locations. Verification deals the DRC (design rule crieterion), making sure the layout obeys all the rules. Layout Simulation checks the layout and makes sure it correctly performs the logic.
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