I am working with a couple of my friends on the design, synthesis and layout generation of a 32 bit pipelined RISC processor. We are implementing circuit level techniques such as clock gating that result in lesser power consumption during switching. However at present we have access to 0.8 micron library files for synthesis and layout purpose and are looking at better technology to make the processor more useful.

I am working on another project using the Berkeley Predictive Model for the 65nm and 45nm MOSFET technologies. I am studying the effect of technology scaling on the leakage and overall power consumption as these are the technology nodes of future and I wish to continue my further research in this field.