I have worked on Fully Depleted Silicon - On - Insulator (SOI) MOSFETs. I have developed a quantitative model for the estimation of the variation in the drain current of a FD SOI due to the thermal gradient induced as the operating temperature of the MOSFET rises. I have also implemented a feedback circuit model that attempts to reduce the above mentioned variation in drain current. A novel device level technique was also proposed that would be better than the existing techniques in attempting to make sure that the SOI devices operate at room temperature.

My other area of interest has been Low Power circuits. I worked on a Ultra Low Power 16-bit RISC processor using 500mV 0.13 micron FD SOI technology. The details of the projects can be found in the link to the projects. I am presently working on exploring the realm of device architecture and their implementation in circuits such as SRAMs for ultra low power applications.