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Publications/Selections for
publications (includes papers under review) in Reverse Chronological
order
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Bansal S.M., Ea T., Amara A. "0.13 micron Fully
Depleted SOI based RISC processor for Ultra Low Power applications."
currently under review at the 33rd International Symposium on Computer
Architecture (ISCA 06), Boston MA, USA. PDF
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Bansal S.M., Nagchoudhry D. "Minimization of
variation in output characteristics of a SOI MOSFET due to self heating"
published in the proceedings of the 2005 IEEE VLSI Design and Test Symposium,
Bangalore, INDIA PDF
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Bansal S.M. "A Quantitative Drain Current Thermal Model
for thermal gradient correction in FD SOI MOS" selected for publication in
the 2004 IEEE International Conference on Microelectronics, Lahore, Pakistan
PDF
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Bansal S.M., Madan A., Gupta N. "Metal T-Gate
structure for Fully Depleted SOI RF-CMOS technology" published in the
proceedings of the 2004 Indian Microelectronics Society Conference, Chandigarh,
INDIA. DOC
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Bansal S.M., Gupta N. "Molecular Digital Logic Circuits"
published in the proceedings of the 1st International Conference on
Advanced Nanotechnology (Oct 2004), Washington DC, USA. abstract
Details of Completed Projects (In Reverse
Chronological Order)
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Developing a Ultra Low Power 16-bit RISC processor based on
the 0.13 micron Fully Depleted SOI technology with 500mV supply voltage. The
processor was used in a security system based on identification using the Iris
of the eye. It incorporated arithmetic, logical and conditional instructions
and the clock to the registers was gated using And gates and control signals
to reduce power consumption during the clock cycles when the registers were
not in use. The multiplexers whose inputs do not change during a particular
clock cycle were not provided the clock pulse to reduce the power consumption
further. The complete VHDL code is
here. A clock period of 24ns was used in the testbench. The project report provides
all the results of synthesis. This project was carried out at
Institut Superieur D`Electronique de Paris
under the guidance of Dr. Amara.
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Implementation of a feedback circuit model as a correcting
circuit for canceling the effects of self heating on the output
characteristics of a SOI MOSFET. Also I proposed a device level correcting
technique that took advantage of the simple fact that increase in temperature
causes changes in threshold voltage and mobility but these changes are such
that they have contradictory effects on the drain current, change in threshold
voltage tries to increase drain current and change in mobility tries to
decrease it. I verified by simulation using HSPICE the possibility of a device
with such an architecture that could negate the effects of changes in Vth and
mobility with the drain current remaining constant even with increase in
temperature. Download ppt
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