Cadence Tutorial - IC layout - Standard Cell creation

Some ideas to keep in mind when designing and creating layouts of the Standard Cells. Standard cells work as building blocks. They must all be the same height if we want to "stack" them on top of each other. The width is of less concern. We can not control both the height and the width the because a large standard cell such as a D flip flop takes up much more room then a small standard cell such as an invertor, thus we fix the height and let the width vary.

The power of standard cells is that by using VHDL or Verilog we can assemble the chip from these building blocks. There are other important aspects to think about when laying out our cells. Here are listed all the options we have chosen when laying out our cell with some explanation of what these options actually do.

Suggested Settings: Here we select the routing style V1H2, which means that all vertical wires will use Metal 1 and all horiztonal wires will use Metal 2.

More Options: here we set the height to 30 microns and let the width vary (-1 means the parameter is free). Thus all our standard cell will have a height of 30 microns.

Pin: This determines where the "pins", output and inputs of the standard cell will be located, in our case we have select both "top" and "bottom" this will make our pins come out both at the top of the standard cell and at the bottom. And we have also chosen to use Metal 1

Routing: Here we changed Over Transistor Routing to none, this helps prevent DRC errors later on. We also chose to use Metal for connections between gates of NMOS and PMOS transistors

Placement: We want the placement of transistors to be optimized, not quick. TOR splitting means that once a drain or gate has reached a certain size it will be split and a second connection will be made. Other wise the current might be limited by small area of a single connection and the current flow would be very low near the edges of the drain or source. We also set the rows to 1, this way a cell can only occupy one row, (ie one can't have a cell 60 um high)

Power/Gnd: Determines the size of the Vdd and Gnd wires, in our case 1.2 um. The merged does not really apply in our case, but is only used if one has a cell that spans two rows, however since we set the rows = 1 in the placement option, this does not concern us.

Process: We made no changes here.