Now that we have created a layout of the standard cell we want to verify that it actually matchs the logic we have in our schematic (transistor level) design. We do this by making sure the net list from SPICE and the simulation match, using the LVS tool in Cadence.
1. From the compacted view go Design >> Save As, name the cell view as "layout"
2. From the compacted view go Tools >> Abstract, then the Abstract menu will be displayed at the top.
3. From the abstarct menu, first select Auto Boundary (Remember to NOT save after you close the menu, as the Auto Boundary will remain, and is difficult to get rid of).
4. In the Set Cell Properties, change Cell Type to standard, and the Cell Shape to L-shape.
4. Now we will generate the abstract, using Abgen, here we change to rules Library to hp14Lib0004 Close and DON'T SAVE (saving will save the autoboundary).
4. Now we also need to create an extracted view. From the compacted view go Verify >> Extract. Make sure the View Name is correct and hit OK.
6. The new view should appear in the Library Manager.
7. Now open both the layout and extracted views from the Library Manager. From the extracted view, go Verify >> LVS.
8. From the LVS window, Hit the Sel by Cursor button then click the cursor anywhere on the extract window, do the same for the schematic window. Make sure that you have the same Library and Cell selected, as shown above. Now hit run and wait for the results. Hopefully we will see this message. Then from the LVS window click on "Output"
Now hit Output. Making sure that the net-lists match. This means the verification was succesful.
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