Cadence Tutorial - IC layout

We now want to simulate the standard cells, using our previous simulation circuit but using the layout to replace the transistor level AND gate.

1. First open the compacted view, and the schematic view. Then from the compacted view, go to Verify >> LVS. From the LVS menu, select "Build Analog". You must run LVS first though as done in Verification

2. After selecting "Build Analog" (at the very bottom of the window), a new window will open up, select eneable all to have all the parasitic capaciatences included

3. After this a new cell view should be created in you library named "analog_extracted"

4. From Library Manger, we go to the cell in which we simulated the Standard Cell, in our case tutorial_and2_4x_test, we need to create a new Cell View, named "config", select the tool "Hierarchy - Editor"

5. Two windows should now open. In the New Hierarchy window, select the Template, in our case HSpice and Verilog, and change the view, from MyView to schematic.

6. In the Hierarchy Editor, RIGHT click the "View to Use" that has analog_extracted next to it. Select "analog_extracted", then click the update button . Then save and exit.

7. Now we have to go the Library Manager and open the config view. Select yes to both options when the window opens.

8. Now from this view, we can simulate the circuit using Analog artist exactly like we did with our schematic. Only in this simulation all capactiances due to interconnects etc. will be accounted for.